Following are the multiple choice questions on Computer Arithmetic based on the UGC-NET syllabus. Computer Arithmetic multiple choice questions.
1) Half adder is an example of ?
BACK NEXT1) Half adder is an example of ?
- Combinational Circuits
- Sequential Circuits
- Asynchronous Circuits
- None of these
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Answer = A
Explanation: Combinational circuits are the circuits whose output depends on the inputs of the same instant of time.
2) In JK flip flop same input, i.e at a particular time or during a clock pulse, the output will oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as ? Explanation: Combinational circuits are the circuits whose output depends on the inputs of the same instant of time.
- Conversion condition
- Race around condition
- Lock out state
- None of these
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Answer = B
Explanation:A race around condition is a flaw in an electronic system or process whereby the output and result of the process is unexpectedly dependent on the sequence or timing of other events.
3) In a JK flip flop, if j=k, the resulting flip flop is referred to as ? Explanation:A race around condition is a flaw in an electronic system or process whereby the output and result of the process is unexpectedly dependent on the sequence or timing of other events.
- D flip flop
- T flip flop
- S-R flip flop
- None of these
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Answer = C
Explanation: In JK flip flop if both the inputs are same then the flip flop behaves like SR flip flop.
4) Master slave flip flop is also referred to as ?
Explanation: In JK flip flop if both the inputs are same then the flip flop behaves like SR flip flop.
4) Master slave flip flop is also referred to as ?
- Level triggered flip flop
- Pulse triggered flip flop
- Edge triggered flip flop
- None of these
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Answer = B
Explanation:The term pulse triggered means the data is entered on the rising edge of the clock pulse, but the output does not reflect the change until the falling edge of clock pulse.
5) Fetch and decode cycle is required in ? Explanation:The term pulse triggered means the data is entered on the rising edge of the clock pulse, but the output does not reflect the change until the falling edge of clock pulse.
- Direct addressing
- Immediate addressing
- Indirect addressing
- None of above
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Answer = B
Explanation:Fetch and decode cycle is required in Immediate addressing because it stores the operand directly on which the operation is performed.
6) Valid bit in each cache is associated with ? Explanation:Fetch and decode cycle is required in Immediate addressing because it stores the operand directly on which the operation is performed.
- Each memory byte in cache
- Each memory word in cache
- One bit with the all memory words
- None of above
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Answer = A
Explanation:No explanation
7) In J-K flip flop the function K=J is used to realize ? Explanation:No explanation
- D flip flop
- S-R flip flop
- T flip flop
- Master slave flip flop
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Answer = D
Explanation: T flip flop allows the same inputs. So if in JK flip flop J = K then it will work as T flip flop.
8) An encoder has 2n input lines and ..... output lines ? Explanation: T flip flop allows the same inputs. So if in JK flip flop J = K then it will work as T flip flop.
- 2
- n
- 2*n
- n*n
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Answer = B
Explanation:No Explanation.
9) ASCII code for alphabet character requires ..... bits ? Explanation:No Explanation.
- 16
- 15
- 8
- 7
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Answer = D
Explanation:No explanation
10) The basic limitation of FSM is that ? Explanation:No explanation
- An FSM can remember arbitrary large amount of information
- An FSM sometimes recognize grammars that are not regular
- It sometimes fails to recognize grammar that are regular
- All of the above comments are true
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Answer = A
Explanation: FSM stands for Finite State Machine.
Explanation: FSM stands for Finite State Machine.
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